National CP3BT26 User Manual

©2004 National Semiconductor Corporation www.national.comCP3BT26 Connectivity Processor with Bluetooth and Dual CAN InterfacesPRELIMINARYMAY 2004CP3BT

www.national.com 10CP3BT26ADC31 I/O ADC Input Channel 3 TSY- Touchscreen Y- contactADC41 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0AD

www.national.com 100CP3BT26MF The Missed SOF bit is set when the framenumber in a valid received SOF does notmatch the expected next value, or when an

101 www.national.comCP3BT26DTGL The DMA Toggle bit is used to determine theinitial state of Automatic DMA (ADMA) opera-tions. Software initially sets

www.national.com 102CP3BT2618.3.20 DMA Mask Register (DMAMSK)Any set bit in the DMAMSK register enables automatic set-ting of the DMA bit in the ALTEV

103 www.national.comCP3BT26receive the next packet. The erroneouspacket is ignored and not transferred viaDMA. If this bit is cleared, automatic error

www.national.com 104CP3BT26FLUSH Writing a 1 to the Flush FIFO bit flushes alldata from the control endpoint FIFOs, resetsthe endpoint to Idle state,

105 www.national.comCP3BT26FLUSH Writing 1 to the Flush bit flushes all data fromthe control endpoint FIFOs, resets the end-point to Idle state, clear

www.national.com 106CP3BT26ACK_STAT The Acknowledge Status bit is valid when theTX_DONE bit is set. The meaning of theACK_STAT bit differs depending o

107 www.national.comCP3BT26TFWL The Transmit FIFO Warning Limit bits specifyhow many more bytes can be transmitted fromthe respective FIFO before an u

www.national.com 108CP3BT2618.3.36 Receive Command Register n (RXCn)Each of the receive endpoints (2, 4, and 6) has one RXCnregister. The registers pr

109 www.national.comCP3BT2619.0 CAN ModuleThe CAN module contains a Full CAN class, CAN (Control-ler Area Network) serial bus interface for low/high s

11 www.national.comCP3BT26PG41 I/O Generic I/O SDAT BT Serial I/F DataPG51 I/O Generic I/O SLE BT Serial I/F Load Enable OutputPG61 I/O Generic I/OWUI

www.national.com 110CP3BT26Figure 34. CAN Block Diagram19.2 BASIC CAN CONCEPTSThis section provides a generic overview of the basic con-cepts of the C

111 www.national.comCP3BT26The CAN protocol allows several transmitting modules tostart a transmission at the same time as soon as they detectthe bus

www.national.com 112CP3BT26Data Length Code (DLC)The DLC field indicates the number of bytes in the data field.It consists of four bits. The data fiel

113 www.national.comCP3BT26A CAN data frame consists of the following fields: Start of Frame (SOF) Arbitration Field + Extended Arbitration Control

www.national.com 114CP3BT26Error FrameAs shown in Figure 40, the Error Frame consists of the errorflag and the error delimiter bit fields. The error f

115 www.national.comCP3BT26Figure 42. Interframe Space19.2.4 Error TypesBit ErrorA CAN device which is currently transmitting also monitorsthe bus. If

www.national.com 116CP3BT26Error ActiveAn error active unit can participate in bus communicationand may send an active (“dominant”) error flag.Error W

117 www.national.comCP3BT2619.2.6 Bit Time LogicIn the Bit Time Logic (BTL), the CAN bus speed and theSynchronization Jump Width can be configured by

www.national.com 118CP3BT26Figure 45. Resynchronization (e > SJW)Figure 46. Resynchronization (e < -SJW)19.2.7 Clock GeneratorThe CAN prescaler

119 www.national.comCP3BT26independent filtering procedure, which provides the possi-bility to establish a BASIC-CAN path.For reception of data frame

www.national.com 12CP3BT26Table 3 CP3BT26 LQFP-144 Signal DescriptionsName Pins I/O Primary FunctionAlternate NameAlternate FunctionX1CKI 1Input 12 MH

www.national.com 120CP3BT26buffer status field. With this lock function, software has thecapability to save several messages with the same identifiero

121 www.national.comCP3BT26All contents of the hidden receive buffer are always copiedinto the respective receive buffer. This includes the receivedme

www.national.com 122CP3BT26Figure 54. Buffer Read Routine (BUFFLOCK Disabled)The first step is only applicable if polling is used to get thestatus of

123 www.national.comCP3BT26CNSTAT status section will be 0101b, as the buffer wasRX_FULL (0100b) before. After finally reading the last re-ceived mess

www.national.com 124CP3BT26ity is combined by the 4-bit TXPRI value and the 4-bit buffernumber (0...14) as shown below. The lowest resulting num-ber r

125 www.national.comCP3BT2619.6.4 TX Buffer StatesThe transmission process can be started after software hasloaded the buffer registers (data, ID, DLC

www.national.com 126CP3BT2619.7.1 Highest Priority Interrupt CodeTo reduce the decoding time for the CIPND register, thebuffer interrupt request with

127 www.national.comCP3BT2619.9 MEMORY ORGANIZATIONThe CAN module occupies 144 words in the memory ad-dress space. This space is organized as 15 banks

www.national.com 128CP3BT2619.10 CAN CONTROLLER REGISTERSTable 51 lists the CAN module registers.19.10.1 Buffer Status/Control Register (CNSTAT)The bu

129 www.national.comCP3BT26Table 52 Buffer Status Section of the CNSTAT RegisterST3 (DIR) ST2 ST1 ST0 (BUSY) Buffer Status000 0RX_NOT_ACTIVE000 1Reser

13 www.national.comCP3BT26ADC31 I/O ADC Input Channel 3 TSY- Touchscreen Y- contactADC41 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0AD

www.national.com 130CP3BT26PRI The Transmit Priority Code field holds thesoftware-defined transmit priority code for themessage buffer.DLC The Data Le

131 www.national.comCP3BT2619.10.3 Storage of Messages with Less Than 8 Data BytesThe data bytes that are not used for data transfer are “don’tcares”.

www.national.com 132CP3BT2619.10.5 Storage of Remote MessagesDuring remote frame transfer, the buffer registers DATA0–DATA3 are “don’t cares”. If a re

133 www.national.comCP3BT2619.10.6 CAN Global Configuration Register (CGCR)The CAN Global Configuration Register (CGCR) is a 16-bitwide register used

www.national.com 134CP3BT26Figure 61. Data Direction Bit ClearSetting the DDIR bit will cause the direction of the data stor-age to be reversed — the

135 www.national.comCP3BT26INTERNAL If the Internal function is enabled, the CANTXand CANRX pins of the CAN module are inter-nally connected to each o

www.national.com 136CP3BT26TSEG1 The Time Segment 1 field configures thelength of the Time Segment 1 (TSEG1). It isnot recommended to configure the ti

137 www.national.comCP3BT2619.10.9 Basic Mask Register (BMSKB/BMSKX)The BMSKB and BMSKX registers allow masking the buffer14, or “don’t care” the inco

www.national.com 138CP3BT2619.10.12 CAN Interrupt Clear Register (CICLR)The CICLR register bits individually clear CAN interruptpending flags caused b

139 www.national.comCP3BT2619.10.15 CAN Error Counter Register (CANEC)The CANEC register reports the values of the CAN ReceiveError Counter and the CA

www.national.com 14CP3BT26PF61 I/O Generic I/OSTD AAI Transmit Data OutputTIO7 Versatile Timer Channel 7PF71 I/O Generic I/OSRD AAI Receive Data Input

www.national.com 140CP3BT26DRIVE The Drive bit shows the output value on theCANTX pin at the time of the error. Note thata receiver will not drive the

141 www.national.comCP3BT26The critical path derives from receiving a remote frame,which triggers the transmission of one or more data frames.There ar

www.national.com 142CP3BT2619.12 USAGE HINTUnder certain conditions, the CAN module receives a framesent by itself, even though the loopback feature i

143 www.national.comCP3BT2620.0 Advanced Audio InterfaceThe Advanced Audio Interface (AAI) provides a serial syn-chronous, full duplex interface to co

www.national.com 144CP3BT2620.2.2 Synchronous ModeIn synchronous mode, the receive and transmit paths of theaudio interface use the same shift clock a

145 www.national.comCP3BT26On the receiver side, only the valid data bits which were re-ceived during the slots assigned to this interface are copiedi

www.national.com 146CP3BT26Figure 69. Accessing Three Devices in Network Mode20.3 BIT CLOCK GENERATIONAn 8-bit prescaler is provided to divide the aud

147 www.national.comCP3BT26Figure 70 shows the interrupt structure of the AAI.Figure 70. AAI Interrupt Structure20.5.3 Normal ModeIn normal mode, each

www.national.com 148CP3BT2620.5.6 Network ModeIn network mode, each frame sync signal marks the begin-ning of new frame. Each frame can consist of up

149 www.national.comCP3BT26If the corresponding Frame Sync Select (FSS) bit in the Au-dio Control and Status register is set, the receive and/ortransm

15 www.national.comCP3BT265.0 CPU ArchitectureThe CP3BT26 uses the CR16C third-generation 16-bitCompactRISC processor core. The CPU implements a Re-du

www.national.com 150CP3BT2620.6.4 IOM-2 ModeThe AAI can operate in a special IOM-2 compatible mode toallow to connect to an external ISDN controller d

151 www.national.comCP3BT2620.6.6 Freeze ModeThe audio interface provides a FREEZE input, which allowsto freeze the status of the audio interface whil

www.national.com 152CP3BT2620.7.1 Audio Receive FIFO Register (ARFR)The Audio Receive FIFO register shows the receive FIFOlocation currently addressed

153 www.national.comCP3BT2620.7.5 Audio Global Configuration Register (AGCR)The AGCR register controls the basic operation of the inter-face. The CPU

www.national.com 154CP3BT26IOM2 The IOM-2 Mode bit selects the normal PCMinterface mode or a special IOM-2 mode usedto connect to external ISDN contro

155 www.national.comCP3BT2620.7.7 Audio Receive Status and Control Register (ARSCR)The ARSCR register is used to control the operation of thereceiver

www.national.com 156CP3BT2620.7.8 Audio Transmit Status and Control Register (ATSCR)The ASCR register controls the basic operation of the inter-face.

157 www.national.comCP3BT2620.7.9 Audio Clock Control Register (ACCR)The ACCR register is used to control the bit timing of the au-dio interface. Afte

www.national.com 158CP3BT2621.0 CVSD/PCM Conversion ModuleThe CVSD/PCM module performs conversion betweenCVSD data and PCM data, in which the CVSD enc

159 www.national.comCP3BT26If the module is only used for PCM conversions, the CVSDclock can be disabled by clearing the CVSD Clock Enablebit (CLKEN)

www.national.com 16CP3BT265.2.4 Interrupt Base Register (INTBASE)The INTBASE register holds the address of the dispatch ta-ble for exceptions. The dis

www.national.com 160CP3BT26The CVSD/PCM module only supports indirect DMA trans-fers. Therefore, transferring PCM data between the CVSD/PCM module and

161 www.national.comCP3BT2621.9.5 Logarithmic PCM Data Input Register (LOGIN)The LOGIN register is an 8-bit wide write-only register. It isused to rec

www.national.com 162CP3BT26DMAPI The DMA Enable for PCM In bit enables hard-ware DMA control for writing PCM data intothe PCMIN register. If cleared,

163 www.national.comCP3BT2622.0 UART ModulesThe CP3BT26 provides four UART modules. Each UARTmodule is a full-duplex Universal Asynchronous Receiver/T

www.national.com 164CP3BT26Data bits are sensed by taking a majority vote of three sam-ples latched near the midpoint of each baud (bit time). Nor-mal

165 www.national.comCP3BT2622.2.2 Synchronous ModeThe synchronous mode of the UART enables the device tocommunicate with other devices using three com

www.national.com 166CP3BT26parity bit is generated and transmitted following the eightdata bits.Figure 80. 8-Bit Data Frame OptionsThe format shown in

167 www.national.comCP3BT26Figure 82 shows a diagram of the interrupt sources and as-sociated enable bits.Figure 82. UART InterruptsThe interrupts can

www.national.com 168CP3BT2622.3 UART REGISTERSSoftware interacts with the UART modules by accessing theUART registers, as listed in Table 70.Table 70

169 www.national.comCP3BT2622.3.1 UART Receive Data Buffer (UnRBUF)The UnRBUF register is a byte-wide, read/write registerused to receive each data by

17 www.national.comCP3BT265.4 CONFIGURATION REGISTER (CFG)The CFG register is used to enable or disable various oper-ating modes and to control option

www.national.com 170CP3BT26UPEN The Parity Enable bit enables or disables par-ity generation and parity checking. When theUART is configured to transm

171 www.national.comCP3BT26UBKD The Break Detect bit indicates when a linebreak condition occurs. This condition is de-tected if RXD remains low for a

www.national.com 172CP3BT2622.3.10 UART Mode Select Register 2 (UnMDSL2)The UnMDSL2 register is a byte-wide, read/write registerthat controls the samp

173 www.national.comCP3BT2622.4.2 Synchronous ModeSynchronous mode is only available for the UART0 module.When synchronous mode is selected and the UC

www.national.com 174CP3BT26Table 72 Baud Rate ProgrammingBaudRateSYS_CLK = 8 MHz SYS_CLK = 6 MHz SYS_CLK = 5 MHz SYS_CLK = 4 MHzO N P %err O N P %err

175 www.national.comCP3BT2623.0 Microwire/SPI InterfaceMicrowire/Plus is a synchronous serial communicationsprotocol, originally implemented in Nation

www.national.com 176CP3BT26Figure 84. Microwire Block Diagram23.1.2 ReadingThe enhanced Microwire interface implements a doublebuffer on read. As illu

177 www.national.comCP3BT2623.2 MASTER MODEIn Master mode, the MSK pin is an output for the shift clock,MSK. When data is written to the MWDAT registe

www.national.com 178CP3BT2623.3 SLAVE MODEIn Slave mode, the MSK pin is an input for the shift clockMSK. MDIDO is placed in TRI-STATE mode when MWCS i

179 www.national.comCP3BT2623.5 MICROWIRE INTERFACE REGISTERSSoftware interacts with the Microwire interface by accessingthe Microwire registers. Ther

www.national.com 18CP3BT265.5 ADDRESSING MODESThe CR16C CPU core implements a load/store architec-ture, in which arithmetic and logical instructions o

www.national.com 180CP3BT26MWDAT register is transmitted on MDIDO,whether or not the data is valid. 0 – Echo back disabled.1 – Echo back enabled.EIO T

181 www.national.comCP3BT2624.0 ACCESS.bus InterfaceThe ACCESS.bus interface module (ACB) is a two-wire se-rial interface compatible with the ACCESS.b

www.national.com 182CP3BT26Acknowledge CycleThe Acknowledge Cycle consists of two signals: the ac-knowledge clock pulse the master sends with each byt

183 www.national.comCP3BT2624.2 ACB FUNCTIONAL DESCRIPTIONThe ACB module provides the physical layer for an AC-CESS.bus compliant serial interface. Th

www.national.com 184CP3BT26Master Bus StallThe ACB module can stall the ACCESS.bus between trans-fers while waiting for the core’s response. The ACCES

185 www.national.comCP3BT26Power DownWhen this device is in Power Save, Idle, or Halt mode, theACB module is not active but retains its status. If the

www.national.com 186CP3BT26NEGACK The Negative Acknowledge bit is set by hard-ware when a transmission is not acknowl-edged on the ninth clock. (In th

187 www.national.comCP3BT26GCMTCH The Global Call Match bit is set in slave modewhen the ACBCTL1.GCMEN bit is set and theaddress byte (the first byte

www.national.com 188CP3BT26INTEN The Interrupt Enable bit controls generatingACB interrupts. When the INTEN bit is clearedACB interrupt is disabled. W

189 www.national.comCP3BT2624.3.7 ACB Own Address Register 1 (ACBADDR1)The ACBADDR1 register is a byte-wide, read/write registerthat holds the module’

19 www.national.comCP3BT265.6 STACKSA stack is a last-in, first-out data structure for dynamic stor-age of data and addresses. A stack consists of a b

www.national.com 190CP3BT2624.4.1 Avoiding Bus Error During Write TransactionA Bus Error (BER) may occur during a write transaction ifthe data registe

191 www.national.comCP3BT26 acb->ACBctl1 |= ACBSTOP; /* Send STOP bit */

www.national.com 192CP3BT2625.0 Timing and Watchdog ModuleThe Timing and Watchdog Module (TWM) generates theclocks and interrupts used for timing peri

193 www.national.comCP3BT2625.3 WATCHDOG OPERATIONThe Watchdog is an 8-bit down counter that operates on therising edge of a specified clock source. A

www.national.com 194CP3BT2625.4.1 Timer and Watchdog Configuration Register (TWCFG)The TWCFG register is a byte-wide, read/write register thatselects

195 www.national.comCP3BT2625.4.4 TWMT0 Control and Status Register (T0CSR)The T0CSR register is a byte-wide, read/write register thatcontrols Timer T

www.national.com 196CP3BT2626.0 Multi-Function TimerThe Multi-Function Timer module contains a pair of 16-bittimer/counters. Each timer/counter unit o

197 www.national.comCP3BT26Counter Clock Source SelectThere are two clock source selectors that allow software toindependently select the clock source

www.national.com 198CP3BT2626.2.1 Mode 1: Processor-Independent PWMMode 1 is the Processor-Independent Pulse Width Modula-tion (PWM) mode, which gener

199 www.national.comCP3BT2626.2.2 Mode 2: Dual Input CaptureMode 2 is the Dual Input Capture mode, which measuresthe elapsed time between occurrences

www.national.com 2CP3BT26Table of Contents1.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 Features . . . . . . . .

www.national.com 20CP3BT26Table 5 Instruction Set SummaryMnemonic Operands DescriptionMOVi Rsrc/imm, Rdest MoveMOVXB Rsrc, Rdest Move with sign extens

www.national.com 200CP3BT2626.2.3 Mode 3: Dual Independent Timer/CounterMode 3 is the Dual Independent Timer mode, which gener-ates system timing sign

201 www.national.comCP3BT2626.2.4 Mode 4: Input Capture Plus TimerMode 4 is the Single Input Capture and Single Timer mode,which provides one external

www.national.com 202CP3BT2626.3 TIMER INTERRUPTSThe Multi-Function Timer unit has four interrupt sources,designated A, B, C, and D. Interrupt sources

203 www.national.comCP3BT2626.5 TIMER REGISTERSTable 79 lists the CPU-accessible registers used to controlthe Multi-Function Timers.26.5.1 Clock Presc

www.national.com 204CP3BT2626.5.5 Reload/Capture A Register (TCRA)The TCRA register is a word-wide, read/write register thatholds the reload or captur

205 www.national.comCP3BT2626.5.8 Timer Interrupt Control Register (TICTL)The TICTL register is a byte-wide, read/write register thatcontains the inte

www.national.com 206CP3BT2627.0 Versatile Timer Unit (VTU)The Versatile Timer Unit (VTU) contains four fully indepen-dent 16-bit timer subsystems. Eac

207 www.national.comCP3BT2627.1.1 Dual 8-bit PWM ModeEach timer subsystem may be configured to generate twofully independent PWM waveforms on the resp

www.national.com 208CP3BT26The two I/O pins associated with a timer subsystem functionas independent PWM outputs in the dual 8-bit PWM mode.If a PWM t

209 www.national.comCP3BT26Figure 108 illustrates the configuration of a timer subsystemwhile operating in capture mode. The numbering inFigure 108 re

21 www.national.comCP3BT26ASHUD Rsrc/imm, RPdest Arithmetic left/right shiftLSHi Rsrc/imm, Rdest Logical left/right shiftLSHD Rsrc/imm, RPdest Logical

www.national.com 210CP3BT2627.2 VTU REGISTERSThe VTU contains a total of 19 user accessible registers, aslisted in Table 81. All registers are word-wi

211 www.national.comCP3BT2627.2.2 I/O Control Register 1 (IO1CTL)The I/O Control Register 1 (IO1CTL) is a word-wide read/write register. The register

www.national.com 212CP3BT26IxCEN The Timer x Interrupt C Enable bit controls in-terrupt requests triggered on the correspond-ing IxCPD bit being set.

213 www.national.comCP3BT2627.2.8 Counter Register n (COUNTx)The Counter (COUNTx) registers are word-wide read/writeregisters. There are a total of fo

www.national.com 214CP3BT2628.0 Register MapTable 82 is a detailed memory map showing the specificmemory address of the memory, I/O ports, and registe

215 www.national.comCP3BT26WTPTC_1SLOT Word 0E F1B0h Write-OnlyWTPTC_3SLOT Word 0E F1B2h Write-OnlyWTPTC_5SLOT Word 0E F1B4h Write-OnlySEQ_RESET Byte

www.national.com 216CP3BT26DMAEV Byte FF FDAAh Read/Write 00hDMAMSK Byte FF FDACh Read/Write 00hMIR Byte FF FDAEh Read/Write 1FhDMACNT Byte FF FDB0h R

217 www.national.comCP3BT26CAN Module Message BuffersCMB0_CNSTAT Word 0E F000h Read/Write XXXXhCMB0_TSTP Word 0E F002h Read/Write XXXXhCMB0_DATA3 Word

www.national.com 218CP3BT26CAN RegistersCGCR Word 0E F100h Read/Write 0000hCTIM Word 0E F102h Read/Write 0000hGMSKX Word 0E F104h Read/Write 0000hGMSK

219 www.national.comCP3BT26BLTC1 Word FF F830h Read/Write 0000hBLTR1 Word FF F834h Read/Write 0000hDMACNTL1 Word FF F83Ch Read/Write 0000hDMASTAT1 B

www.national.com 22CP3BT26RETX Return from exceptionPUSH imm, Rsrc, RA Push “imm” number of registers on user stack, starting with Rsrc and possibly i

www.national.com 220CP3BT26System ConfigurationMCFG Byte FF F910h Read/Write 00hDBGCFG Byte FF F912h Read/Write 00hMSTAT Byte FF F914h Read Only ENV2:

221 www.national.comCP3BT26FSMTRAN Byte FF F754h Read/Write 30hFSMPROG Byte FF F756h Read/Write 16hFSMPERASE Byte FF F758h Read/Write 04hFSMMERASE0 By

www.national.com 222CP3BT26Power ManagementPMMCR Byte FF FC60h Read/Write 00hPMMSR Byte FF FC62h Read/Write 0000 0XXXbMulti-Input Wake-Up 0WK0EDG Word

223 www.national.comCP3BT26PCDIR Byte FF FB12h Read Only 00hPCDIN Byte FF FB14h Read/Write XXhPCDOUT Byte FF FB16h Read/Write XXhPCWPU Byte FF FB18h R

www.national.com 224CP3BT26PJDIN Byte FF F344h Read Only XXhPJDOUT Byte FF F346h Read/Write XXhPJWPU Byte FF F348h Read/Write 00hPJHDRV Byte FF F34Ah

225 www.national.comCP3BT26Microwire/SPI InterfaceMWDAT Word FF F3A0h Read/Write XXXXhMWCTL1 Word FF F3A2h Read/Write 0000hMWSTAT Word FF F3A4h Read O

www.national.com 226CP3BT26UART2U2TBUF Byte FF F240h Read/Write XXhU2RBUF Byte FF F242h Read Only XXhU2ICTRL Byte FF F244h Read/Write 01h Bits 0:1 rea

227 www.national.comCP3BT26ACCESS.busACBSDA Byte FF F2A0h Read/Write XXhACBST Byte FF F2A2h Read/Write 00hACBCST Byte FF F2A4h Read/Write 00hACBCTL1 B

www.national.com 228CP3BT26Versatile Timer UnitMODE Word FF FF80h Read/Write 0000hIO1CTL Word FF FF82h Read/Write 0000hIO2CTL Word FF FF84h Read/Write

229 www.national.comCP3BT26RNGRNGCST Word FF F280h Read/Write 0000hRNGD Word FF F282h Read/Write 0000hRNGDIVH Word FF F284h Read/Write 0000hRNGDIVL Wo

23 www.national.comCP3BT26STORMP imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R7,R6)DI Disable maskable interruptsEI Enable mask

www.national.com 230CP3BT2629.0 Register Bit FieldsThe following tables show the functions of the bit fields of the device registers. For more informa

231 www.national.comCP3BT26WTPTC_5SLOT[15:8] WTPTC_5SLOT[15:8]SEQ_RESET ReservedSEQ_RESETSEQ_CONTINUE ReservedSEQ_CONTINUERX_STATUS Reserved HEC Error

www.national.com 232CP3BT26NAKEV OUT INNAKMSK OUT INFWEV RXWARN[3:1] Reserved TXWARN[3:1] ReservedFWMSK RXWARN[3:1] Reserved TXWARN[3:1] ReservedFNH M

233 www.national.comCP3BT26RXS2 RX_ERR SETUP TOGGLE RX_LAST RCOUNTRXC2 Reserved RFWL Reserved FLUSHIGN_SETUPReserved RX_ENEPC5 STALL Reserved ISO EP_E

www.national.com 234CP3BT26CANMemoryRegisters15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CMBn.ID1XI28ID10XI27ID9XI26ID8XI25ID7XI24ID6XI23ID5XI22ID4XI21ID3XI2

235 www.national.comCP3BT26System Configuration Registers76543210MCFGReservedMEM_IO_SPEEDMISC_IO_SPEEDUSB_ENABLESCLKOE MCLKOE PLLCLKOE EXIOEDBGCFG Res

www.national.com 236CP3BT26FMPROG Reserved FTPROGFMPERASE Reserved FTPERFMMERASE0 Reserved FTMERFMEND Reserved FTENDFMMEND Reserved FTMENDFMRCV Reserv

237 www.national.comCP3BT26FSMAR0 ReservedUSB_EN-ABLEFSMAR1 WRPROTRDPROT ISPE EMPTY BOOTAREAFSMAR2 CADR15:0Flash Data Memory Interface Registers15 14

www.national.com 238CP3BT26PMM Register76543210PMMCR HCCH HCCM DHC DMC WBPSM HALT IDLE PSMPMMSR Reserved OHC OMC OLCMIWU16Registers15 14 13 12

239 www.national.comCP3BT26ATDR1 ATDH ATDLATDR2 ATDH ATDLATDR3 ATDH ATDLAGCRCLKENAAIENIOM2 IFS FSL CTF CRF IEBC FSS IEFS SCS LPB DWL ASSAISCR Reserved

www.national.com 24CP3BT266.0 MemoryThe CP3BT26 supports a uniform 16M-byte linear addressspace. Table 6 lists the types of memory and peripheralsthat

www.national.com 240CP3BT26MWSPI16Registers15 . . . 9876543210MWDAT MWDATMWCTL1 SCDV SCIDL SCM EIW EIR EIO ECHO MOD MNS MWENMWSTAT Reserved OVR RBF BS

241 www.national.comCP3BT26VTURegisters151413121110 9876543210MODE TMOD4T8RUNT7RUNTMOD3T6RUNT5RUNTMOD2T4RUNT3RUNTMOD1T2RUNT1RUNIO1CTLP4POLC4EDGP3PO

www.national.com 242CP3BT26RNGRegisters15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RNGCST Reserved IMSK ReservedDVALIDRNGERNGD RNGDRNGDIVH ReservedRNGDIV17:1

243 www.national.comCP3BT2630.0 Electrical Characteristics30.1 ABSOLUTE MAXIMUM RATINGSIf Military/Aerospace specified devices are required, pleasecon

www.national.com 244CP3BT26IO(Off)Output Leakage Current(I/O pins in input mode) 0V ≤ Vout ≤ Vcc -2.0 2.0 µAIcca1 Digital Supply Current Active Mode b

245 www.national.comCP3BT2630.3 USB TRANSCEIVER ELECTRICAL CHARACTERISTICS (Temperature: -40°C ≤ TA ≤ +85°C)30.4 ADC ELECTRICAL CHARACTERISTICS (Tempe

www.national.com 246CP3BT2630.5 FLASH MEMORY ON-CHIP PROGRAMMINGSymbol Parameter Conditions Min Max UnitstSTARTProgram/Erase to NVSTR Setup Timea(

247 www.national.comCP3BT2630.6 OUTPUT SIGNAL LEVELSAll output signals are powered by the digital supply (VCC). Table 83 summarizes the states of the

www.national.com 248CP3BT26Figure 110. Clock TimingFigure 111. NMI Signal TimingFigure 112. Non-Power-On ResetFigure 113. Power-On ResetX1CKItX1htX1lt

249 www.national.comCP3BT2630.8 UART TIMINGFigure 114. UART Asynchronous Mode TimingTable 85 UART SignalsSymbolFigureDescription Reference Min (ns) Ma

25 www.national.comCP3BT266.2 BUS INTERFACE UNIT (BIU)The BIU controls the interface between the CPU core busand those on-chip modules which are mappe

www.national.com 250CP3BT2630.9 I/O PORT TIMINGFigure 115. I/O Port TimingTable 86 I/O Port SignalsSymbolFigureDescription Reference Min (ns) Max (ns)

251 www.national.comCP3BT2630.10 ADVANCED AUDIO INTERFACE (AAI) TIMINGFigure 116. Receive Timing, Short Frame SyncTable 87 Advanced Audio Interface (A

www.national.com 252CP3BT26Figure 117. Transmit Timing, Short Frame SyncFigure 118. Receive Timing, Long Frame SyncFigure 119. Transmit Timing, Long F

253 www.national.comCP3BT2630.11 MICROWIRE/SPI TIMINGTable 88 Microwire/SPI SignalsSymbolFigureDescription Reference Min (ns) Max (ns)Microwire/SPI In

www.national.com 254CP3BT26Figure 120. Microwire Transaction Timing, Normal Mode, SCIDL = 0tMDOv120 Microwire Data Out ValidNormal Mode: After FE on M

255 www.national.comCP3BT26Figure 121. Microwire Transaction Timing, Normal Mode, SCIDL = 1lsbmsbtMSKptMSKhtMDlhtMDlstMCSstMCShtMSKstMDOftMDOvtMDOftMD

www.national.com 256CP3BT26Figure 122. Microwire Transaction Timing, Alternate Mode, SCIDL = 0MSKlsbmsbData InlsbmsbMDODO(master)lsbmsbMDIDO(slave)MCS

257 www.national.comCP3BT26Figure 123. Microwire Transaction Timing, Alternate Mode, SCIDL = 1Figure 124. Microwire Transaction Timing, Data Echoed to

www.national.com 258CP3BT2630.12 ACCESS.BUS TIMINGTable 89 ACCESS.bus SignalsSymbolFigureDescription Reference Min (ns) Max (ns)ACCESS.bus Input Signa

259 www.national.comCP3BT26Figure 125. ACB Signals (SDA and SCL) TimingFigure 126. ACB Start and Stop Condition TimingFigure 127. ACB Start Condition

www.national.com 26CP3BT266.4.2 I/O Zone Configuration Register (IOCFG)The IOCFG register is a word-wide, read/write register thatcontrols the timing

www.national.com 260CP3BT26Figure 128. ACB Data TimingtSCAvotSDAhtCSLlowtSDAsitSCLhighSCLSDANote: In the timing tables the parameter name is added wit

261 www.national.comCP3BT2630.13 USB PORT AC CHARACTERISTICS30.14 MULTI-FUNCTION TIMER (MFT) TIMINGFigure 129. Multi-Function Timer Input TimingTable

www.national.com 262CP3BT2630.15 VERSATILE TIMING UNIT (VTU) TIMINGFigure 130. Versatile Timing Unit Input TimingTable 92 Versatile Timing Unit Input

263 www.national.comCP3BT2630.16 EXTERNAL BUS TIMINGTable 93 External Bus SignalsSymbolFigureDescription Reference Min (ns) Max (ns)External Bus Input

www.national.com 264CP3BT26Figure 131. Early Write Between Normal Read Cycles (No Wait States)T1 T2 T1 T2 T3 T1 T2A[21:0]A22 ('13 only)CLKNormal

265 www.national.comCP3BT26Figure 132. Late Write Between Normal Read Cycles (No Wait States)T1 T2 T1 T2 T1 T2CLKSELxD[15:0]In InOut(y ≠ x)RDNormal Re

www.national.com 266CP3BT26Figure 133. Consecutive Normal Read Cycles (Burst, No Wait States)T1 T2 T2B T1 T2 T2BNormal Read Normal ReadCLKSELxSELyWR[1

267 www.national.comCP3BT26Figure 134. Normal Read Cycle (Wait Cycle Followed by Hold Cycle)T1 TW T2 THCLKD[15:0]SELn,SELIOWR[1:0]RDt4t5, t12t5, t12t5

www.national.com 268CP3BT26Figure 135. Early Write Between Fast Read CyclesTidleT1-2 T1 T1T2 T3 T1-2Fast Read Early WriteCLKSELxSELyWR[1:0]D[15:0](y ≠

269 www.national.comCP3BT2631.0 Pin Assignments31.1 LQFP-128 PACKAGEFor 128-pin devices, Figure 136 provides a pinout diagram, and Table 94 provides t

27 www.national.comCP3BT26IPRE The Preliminary Idle bit controls whether anidle cycle is inserted prior to the current buscycle, when the new bus cycl

www.national.com 270CP3BT26AVCC 29 PWRADGND 90 PWRADVCC 89 PWRUVCC 62 PWRUGND 63 PWRX2CKI 30 IX2CKO 31 OENV2 SLOWCLK 34 I/OENV1 CPUCLK 35 I/OENV0 PLLC

271 www.national.comCP3BT26PC5 D13 5 GPIOPC6 D14 3 GPIOPC7 D15 2 GPIOPE0 RXD0 87 GPIOPE1 TXD0 83 GPIOPE2 RTS86 GPIOPE3 CTS88 GPIOPE4 CKX/TB 40 GPIOPE5

www.national.com 272CP3BT2631.2 LQFP-144 PACKAGEFor 144-pin devices, Figure 137 provides a pinout diagram, and Table 95 provides the pin assignments.

273 www.national.comCP3BT26Table 95 Pin Assignments for LQFP-144 PackagePin Name Alternate Function(s) Pin Number TypeGND 23, 32, 58, 85, 91, 121 PWR

www.national.com 274CP3BT26PB4 D4 17 GPIOPB5 D5 15 GPIOPB6 D6 14 GPIOPB7 D7 13 GPIOPC0 D8 11 GPIOPC1 D9 10 GPIOPC2 D10 8 GPIOPC3 D11 7 GPIOPC4 D12 5 G

275 www.national.comCP3BT26A22 62 OA21 61 OA20 60 OA19 54 OA18 53 OA17 45 OA16 42 OA15 40 OA14 39 OA13 143 OA12 142 OA11 141 OA10 139 OA9 132 OA8 131

www.national.com 276CP3BT2632.0 Revision HistoryTable 96 Revision History Date Major Changes From Previous Version4/3/03 Original release.5/26/03Fixed

277 www.national.comCP3BT2633.0 Physical Dimensions (millimeters) unless otherwise notedFigure 138. LQFP-128 PackageFigure 139. LQFP-144 Package

National Semiconductor Americas CustomerSupport CenterEmail: [email protected]: 1-800-272-9959National Semiconductor Europe CustomerSupport Cent

www.national.com 28CP3BT26FRE The Fast Read Enable bit controls whetherfast read bus cycles are used. A fast read op-eration takes one clock cycle. A

29 www.national.comCP3BT267.0 System Configuration RegistersThe system configuration registers control and provide sta-tus for certain aspects of devi

3 www.national.comCP3BT262.0 FeaturesCPU Features Fully static RISC processor core, capable of operatingfrom 0 to 24 MHz with zero wait/hold states

www.national.com 30CP3BT267.2 MODULE STATUS REGISTER (MSTAT)The MSTAT register is a byte-wide, read-only register thatindicates the general status of

31 www.national.comCP3BT268.0 Flash MemoryThe flash memory consists of the flash program memoryand the flash data memory. The flash program memory isf

www.national.com 32CP3BT268.2.1 Main Block 0 and 1Main Block 0 and Main Block 1 hold the 256K-byte programspace, which consists of the Boot Area and C

33 www.national.comCP3BT268.3.3 Main Block Page EraseA flash erase operation sets all of the bits in the erased re-gion. Pages of a main block can be

www.national.com 34CP3BT268.4 INFORMATION BLOCK WORDSTwo words in the information blocks are dedicated to holdsettings that affect the operation of th

35 www.national.comCP3BT26RDPROT The RDPROT field controls the global readprotection mechanism for the on-chip flashprogram memory. If a majority of t

www.national.com 36CP3BT268.5.1 Flash Memory Information Block Address Register (FMIBAR/FSMIBAR)The FMIBAR register specifies the 8-bit address for re

37 www.national.comCP3BT268.5.5 Flash Data Memory 0 Write Enable Register (FSM0WER)The FSM0WER register controls write protection for theflash data me

www.national.com 38CP3BT268.5.7 Flash Memory Status Register (FMSTAT/FSMSTAT)This register reports the currents status of the on-chip Flashmemory. The

39 www.national.comCP3BT268.5.10 Flash Memory Transition Time Reload Register (FMTRAN/FSMTRAN)The FMTRAN/FMSTRAN register is a byte-wide read/writereg

www.national.com 4CP3BT263.0 Device OverviewThe CP3BT26 connectivity processor is a complete micro-computer with all system timing, interrupt logic, p

www.national.com 40CP3BT268.5.16 Flash Memory Recovery Time Reload Register (FMRCV/FSMRCV)The FMRCV/FSMRCV register is a byte-wide read/writeregister

41 www.national.comCP3BT269.0 DMA ControllerThe DMA Controller (DMAC) has a register-based program-ming interface, as opposed to an interface based on

www.national.com 42CP3BT26Direct mode supports two bus policies: intermittent and con-tinuous. In intermittent mode, the DMAC gives bus master-ship ba

43 www.national.comCP3BT26If the DMASTAT.VLD bit is clear:1. The transfer operation terminates.2. The channel sets the DMASTAT.OVR bit.3. The DMASTAT.

www.national.com 44CP3BT269.6.1 Device A Address Counter Register (ADCAn)The Device A Address Counter register is a 32-bit, read/write register. It ho

45 www.national.comCP3BT269.6.6 Block Length Register (BLTRn)The Block Length register is a 16-bit, read/write register. Itholds the number of DMA tra

www.national.com 46CP3BT269.6.8 DMA Status Register (DMASTAT)The DMA status register is a byte-wide, read register thatholds the status information fo

47 www.national.comCP3BT2610.0 InterruptsThe Interrupt Control Unit (ICU) receives interrupt requestsfrom internal and external sources and generates

www.national.com 48CP3BT2610.3.1 Interrupt Vector Register (IVCT)The IVCT register is a byte-wide read-only register which re-ports the encoded value

49 www.national.comCP3BT2610.3.4 Interrupt Enable and Mask Register 0 (IENAM0)The IENAM0 register is a word-wide read/write registerwhich holds bits t

5 www.national.comCP3BT263.7 BLUETOOTH LLCThe integrated hardware Bluetooth Lower Link Controller(LLC) complies to the Bluetooth Specification Version

www.national.com 50CP3BT2610.4 MASKABLE INTERRUPT SOURCESTable 20 shows the interrupts assigned to various on-chipmaskable interrupts. The priority of

51 www.national.comCP3BT2611.0 Triple Clock and ResetThe Triple Clock and Reset module generates a 12 MHzMain Clock and a 32.768 kHz Slow Clock from e

www.national.com 52CP3BT2611.1 EXTERNAL CRYSTAL NETWORKAn external crystal network is connected to the X1CKI andX1CKO pins to generate the Main Clock,

53 www.national.comCP3BT26Choose capacitor component values in the tables to obtainthe specified load capacitance for the crystal when com-bined with

www.national.com 54CP3BT2611.5 SYSTEM CLOCKThe System Clock drives most of the on-chip modules, in-cluding the CPU. Typically, it is driven by the Mai

55 www.national.comCP3BT26FCLK bit cannot be cleared until the PLL clockhas stabilized. After reset this bit is set.0 – PLL is active.1 – PLL is power

www.national.com 56CP3BT2612.0 Power ManagementThe Power Management Module (PMM) improves the effi-ciency of the CP3BT26 by changing the operating mod

57 www.national.comCP3BT2612.3 IDLE MODEIn Idle mode, the System Clock is disabled and therefore theclock is stopped to most modules of the device. Th

www.national.com 58CP3BT26HALT The Halt Mode bit indicates whether the de-vice is in Halt mode. Before entering Haltmode, the WBPSM bit must be set. W

59 www.national.comCP3BT2612.6.2 Power Management Status Register (PMMSR)The Management Status Register (PMMR) is a byte-wide,read/write register that

www.national.com 6CP3BT263.14 RANDOM NUMBER GENERATOR RNG peripheral for use in Trusted Computer Peripheral Ap-plications (TCPA) to improve the authen

www.national.com 60CP3BT2612.7.2 Entering Idle ModeEntry into Idle mode is performed by writing a 1 to the PM-MCR.IDLE bit and then executing a WAIT i

61 www.national.comCP3BT2613.0 Multi-Input Wake-UpThe Multi-Input Wake-Up (MIWU) unit consists of two iden-tical 16-channel modules. Each module can a

www.national.com 62CP3BT2613.1 MULTI-INPUT WAKE-UP REGISTERSTable 28 lists the MIWU registers.Table 27 MIWU SourcesMIWU Channel SourceWUI0 TWM T0OUTWU

63 www.national.comCP3BT2613.1.1 Wake-Up Edge Detection Register (WK0EDG)The WK0EDG register is a word-wide read/write registerthat controls the edge

www.national.com 64CP3BT2613.1.7 Wake-Up Interrupt Control Register 1 (WK0ICTL1)The WK0ICTL1 register is a word-wide read/write registerthat selects t

65 www.national.comCP3BT2613.1.11 Wake-Up Pending Register (WK0PND)The WK0PND register is a word-wide read/write register inwhich the Multi-Input Wake

www.national.com 66CP3BT2613.2 PROGRAMMING PROCEDURESTo set up and use the Multi-Input Wake-Up function, use thefollowing procedure. Performing the st

67 www.national.comCP3BT2614.0 Input/Output PortsEach device has up to 54 software-configurable I/O pins, or-ganized into 8-bit ports (not all bits ar

www.national.com 68CP3BT26In the descriptions of the ports and port registers, the lower-case letter “x” represents the port designation, either B, C,

69 www.national.comCP3BT26All of the port registers are byte-wide read/write registers,except for the port data input registers, which are read-onlyre

7 www.national.comCP3BT263.21 POWER MANAGEMENTThe Power Management Module (PMM) improves the effi-ciency of the device by changing the operating mode

www.national.com 70CP3BT2614.1.6 Port High Drive Strength Register (PxHDRV)The PxHDRV register is a byte-wide, read/write register thatcontrols the sl

71 www.national.comCP3BT2614.2 OPEN-DRAIN OPERATIONA port pin can be configured to operate as an invertingopen-drain output buffer. To do this, the CP

www.national.com 72CP3BT2615.0 Bluetooth ControllerThe integrated hardware Bluetooth Lower Link Controller(LLC) complies to the Bluetooth Specificatio

73 www.national.comCP3BT26transmitter circuit of the radio chip is enabled, correspond-ing to the settings of the power control register in the radioc

www.national.com 74CP3BT26Write OperationWhen the R/W bit is clear, the 16 bits of the data field areshifted out of the CP3BT26 on the falling edge of

75 www.national.comCP3BT26Figure 18. 32-Bit Write TimingFigure 19. 32-Bit Read TimingAn example of a 32-bit write is shown in Table 31. In this ex-amp

www.national.com 76CP3BT2615.3 LMX5251 POWER-UP SEQUENCETo power-up a Bluetooth system based on the CP3BT26and LMX5251 devices, the following sequence

77 www.national.comCP3BT26Figure 22. LMX5252 Power-Up Sequence15.5 BLUETOOTH SLEEP MODEThe Bluetooth controller is capable of putting itself into asle

www.national.com 78CP3BT2615.8 BLUETOOTH SHARED DATA RAMThe shared data RAM is a 4.5K memory-mapped section ofRAM that contains the link control data,

79 www.national.comCP3BT2616.0 12-Bit Analog to Digital ConverterThe integrated 12-bit ADC provides the following features: 8-input analog multiplexe

www.national.com 8CP3BT264.0 Signal DescriptionsFigure 1. CP3BT26 Device SIgnalsSome pins may be enabled as general-purpose I/O-portpins or as alterna

www.national.com 80CP3BT26The output of the Input Multiplexer is available externally asthe MUXOUT0 and MUXOUT1 signals. In single-endedmode, only MUX

81 www.national.comCP3BT2616.2 TOUCHSCREEN INTERFACEThe ADC provides an interface for 4-wire resistive touch-screens with the resolution necessary for

www.national.com 82CP3BT2616.2.2 Measuring Pen ForceFigure 27 shows equivalent circuits for the driver modesused to measure the X, Y, and Z coordinate

83 www.national.comCP3BT263. By extension, the ADC negative voltage reference canbe internally connected to the TSY- terminal, to recoverthe full 4096

www.national.com 84CP3BT2616.5.1 ADC Global Configuration Register (ADCGCR)The ADCGCR register controls the basic operation of the in-terface. The CPU

85 www.national.comCP3BT26PREF_CFG The Positive Voltage Reference Configurationfield specifies the source of the ADC positivevoltage reference, accord

www.national.com 86CP3BT2616.5.3 ADC Conversion Control Register (ADCCNTRL)The ADCCNTRL register specifies the trigger conditions foran ADC conversion

87 www.national.comCP3BT2616.5.6 ADC Result Register (ADCRESLT)The ADCRESLT register includes the software-visible endof a 4-word FIFO. Conversion res

www.national.com 88CP3BT2617.0 Random Number Generator (RNG)The RNG unit is a hardware “true random” number genera-tor. When enabled, this unit provid

89 www.national.comCP3BT2617.2 RANDOM NUMBER GENERATOR REGISTER SETTable 34 lists the RNG registers.17.2.1 RNG Control and Status Register (RNGCST)The

9 www.national.comCP3BT26Table 2 CP3BT26 LQFP-128 Signal DescriptionsName Pins I/O Primary FunctionAlternate NameAlternate FunctionX1CKI 1Input 12 MHz

www.national.com 90CP3BT2618.0 USB ControllerThe CR16 USB node is an integrated USB node controllerthat features enhanced DMA support with many automa

91 www.national.comCP3BT2618.2 ENDPOINT OPERATION18.2.1 Address Detection Packets are broadcast from the host controller to all nodeson the USB networ

www.national.com 92CP3BT26Bidirectional Control Endpoint FIFO0 OperationFIFO0 should be used for the bidirectional control endpoint0. It can be config

93 www.national.comCP3BT26Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3)The Receive FIFOs for endpoints 2, 4, and 6 support bulk,interrup

www.national.com 94CP3BT2618.3.1 Main Control Register (MCNTRL)The MCNTRL register controls the main functions of theCR16 USB node. The MCNTRL registe

95 www.national.comCP3BT26NAT The Node Attached indicates that this node isready to be detected as attached to USB.When clear, the transceiver forces

www.national.com 96CP3BT2618.3.3 Main Event Register (MAEV)The Main Event Register summarizes and reports the mainevents of the USB transactions. This

97 www.national.comCP3BT26SD3 The Suspend Detect 3 ms bit is set after 3 msof IDLE have been detected on the upstreamport, indicating that the device

www.national.com 98CP3BT2618.3.9 Receive Event Register (RXEV) The RXEV register reports the current status of the FIFO,used by the three Receive Endp

99 www.national.comCP3BT2618.3.13 FIFO Warning Event Register (FWEV) The FWEV register signals whether a receive or transmitFIFO has reached its warni